1. Field of the Invention
This invention is related to the field of digital communications and, more particularly, to the test and debug of digital systems.
2. Description of the Related Art
As dependence on various electronic systems continues to increase, so too does the need for reliability. From a hardware perspective, reliability may be ascertained by testing at various levels. These levels of testing include system tests, printed circuit assembly (i.e. circuit board) tests and integrated circuit tests. Such tests seek to ensure proper fabrication and assembly of the various components of the system.
Numerous well known methods of test and debug exist for the purpose of debugging circuits and systems. One such method is boundary scan. Generally speaking, boundary scan involves accessing and stimulating a chip or subsystem via external pins to perform internal test functions on the device. Scan registers are then used to capture state from device input and output pins. Boundary scan typically involves driving a unique pattern over all wires at low speed and utilizing signature analysis to detect errors. Another method is to incorporate “built-in self test” (BIST) functionality into the design of a computer system. BIST involves moving test functionality directly onto the chip itself. With BIST functionality designed into a system, many test procedures may be accomplished at a higher speed than is otherwise possible. For example, by running tests at circuit speeds the duration of a test may be reduced. In addition BIST may enable the ability to do in-system tests, without the need for external test equipment. Other advantages of BIST may include simplifying any required external test equipment and reducing the cost and effort of generating test patterns and simulating faults.
As fabrication and miniaturization techniques advance, the possibility of certain defects in the fabricated part may increase. One such defect is called a bridge. FIG. 1 provides an example of a bridge fault in a fabricated part. FIG. 1 shows an integrated circuit 100 which has been fabricated and packaged using ball grid array (BGA) technology. BGA is a well known technology which enables high density, high I/O count packaging. Illustrated in FIG. 1 is an exploded view 102 of a portion of chip 100. View 102 shows an array of contact points, or balls, which are configured to transmit and/or receive signals. Generally speaking, when properly manufactured, each of the contact points should be electrically isolated from one another. For example, contact points 110 illustrate an even spacing around each point 110. However, two bridge defects 105 and 106 can be seen in view 102. A bridge 105 has been created between contact points 103 and 104. Also, a bridge 106 may be seen between contact points 108 and 109. These bridge defects results in an inability to simultaneously send and/or receive distinct signals from the bridged contact points. Consequently, errors in operation typically results.
While the illustration in FIG. 1 illustrates a bridge defect in a BGA, other manufacturing techniques may similarly result in bridge type defects. Whether BIST is used, or some other type of testing, detecting interconnect and/or bridge type defects is of great importance.
What is desired is a method and mechanism for detecting interconnect and bridge type faults.